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AN1150/0799 1/40 application note benchmark st72 vs. pic16 by microcontroller division application team abstract this document presents the results of a competitive analysis between the stmicroelectonics st72254 and the microchip pic16f876. these two microcontrollers (mcus) have been chosen for comparison because they are in a similar performance category and were introduced on the market at the same time. the comparison of the two mcus is divided into two major parts. first the cores, with a comparison of their architecture including performance benchmarks. these benchmarks are based on assembler and c routines that are representative of typical microcontroller applications. the second part examines the peripherals in terms of their functionality and to what extent they off-load the core and the driver software. finally, you will find a table summarizing the weak and the strong points of each mcu. two files are appended to this document, you can find them in our web server (mcu.st.com) in the application note section. the first one entitled performance comparison between st72254 and pic16f876 includes the results given in this document plus the description of the source and the compilation options used. this file was created in order to allow you to easily reproduce the benchmark. the second file regroups all the source files used. the information on the pic16f876 is based on the microchip datasheet: ds30292a.pdf 1a
2/40 table of contents 40 1 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.5 voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.6 stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.8 addressing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.9 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.10 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.11 power saving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.12 power consumption data (taken from the datasheet) . 12 3 core performance comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 assembler test routines overview . . . . . . . . . . . . . . . . . . . . 15 3.2 assembler test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 results analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 c test routines overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 c test results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4 peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4 wdt: watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.5 lvd: low voltage detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.6 adc: analog to digital converter . . . . . . . . . . . . . . . . . . . . . . 28 4.7 spi serial communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.8 i2c serial communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9 usart/sci serial communication (pic16f87x only) . . . . . . . 33 4.10 isp: in situ programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.11 in circuit debu gging (pic16f87x only) . . . . . . . . . . . . . . . . . . . 35 4.12 reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.13 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5 device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6 weak / strong points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2
3/40 benchmark st72 vs. pic16 1 device description table 1. microchip pic16c62b pic16c72a pic16f873 pic16f876 program memory 2k*14 2k*14 4k*14 (flash) 8k*14 (flash) ram 128*8 128*8 192*8 128*8 eeprom 368*8 128*8 eeprom stack 8*13-bit, can store up to 8 addresses cpu frequency up to 5mhz (with 20mhz oscillator) oscillator rc / ceramic / crystal power saving one mode (sleep mode) operating range 0c to +70c or -40c to +85c (optional -40c to +125c on 16c62b or 16c72a but not on 16f87x) package so28/pdip28 (windowed version available for 16c62b or 16c72a) i/o port 22 pins with individual direction control. output are push-pull (except 1 true open- drain pin). 8 pins may have internal pull-up (globally selected). current up to 25ma. watchdog on-chip rc and a 8-bit prescaler (the prescaler is shared with timer0). the time- out period may vary between 7ms and 4.2s. but due to the internal rc variations, the time-out period is between 896ms and 4.2s for the same settings. timer 8-bit timer/counter with 8-bit prescaler (shared with wdt) 16-bit timer/counter with prescaler, internal/external clock and possible dedicated oscillator. 8-bit timer with 8-bit period register, prescaler and postscaler (this timer does not support external clock despite what is described in the microchip datasheet) serial communication spi, i2c spi, i2c spi/i2c,sci adc no 8-bit with 5 inputs 10-bit with 5 inputs lvd selectable, one level (known as bor in the microchip documentation) reset wdt, por, lvd, external. during internal reset (wdt, lvd or por) the reset state is not externally visible) isp m clr ,clk,data (need 12v on m clr ) two modes: the old one, and a new +5v only mode (it needs one more pin)
4/40 benchmark st72 vs. pic16 table 2. stmicroelectronics st72104g1 st72104g2 st72216g1 st72215g2 st72254g1 st72254g2 program memory 4k*8 (flash) 8k*8 (flash) 4k*8 (flash) 8k*8 (flash) 4k*8 (flash) 8k*8 (flash) ram 256*8 256*8 256*8 256*8 256*8 256*8 stack 128*8 128*8 128*8 128*8 128*8 128*8 oscillator rc / ceramic / crystal / internal / clock security system (clk filter, safe oscillator, limitation detection) power saving four power saving modes cpu frequency up to 8mhz (with 16mhz oscillator) operating range -40c to +85c (optional -40c to +125c) package so28/sdip32 i/o port 22 pins with individual direction control and individual mode control (push-pull, open-drain, input with or without pull up). open drain mode is limited to logic level except for pa4 and pa6, which are true open drain pins. watchdog 64 values selectable for time-out from 1.5ms to 98ms @ fcpu=8mhz timer one 16-bit timer/counter with 2 ic, 2 oc, 1 pwm one 16-bit timer/counter with 2 ic, 2 oc, 1 pwm one 16-bit timer with 2 ic, 2 oc, 1 pwm serial communication spi spi spi, i2c spi, i2c adc no no 8-bit with 6 inputs lvd 3 selectable levels reset wdt, por, lvd, external. during internal reset (wdt, lvd or por), the reset state is externally visible (reset pin in low state). internal pull-up. isp reset, ispsel, ipsclk, ipsdata
5/40 benchmark st72 vs. pic16 2 core 2.1 architecture ? pic16 the pic16 family is based on a harvard architecture (i.e.: data and program memory spaces are separated). these processors have a risc core ( reduced instruction set computer ) with only 35 instructions. all these instructions have the same size: 14 bits (for the pic16 family). they are executed in one cpu cycle except branches which need two cycles. the processor uses an accumulator called w (working register). despite its harvard architecture, the pic16f87x program memory is readable and writable by the mcu during program execution. but the access method is not simple. this means, it is not efficient to store data tables directly in program memory. ? st72 the st72 family is based on a von neuman architecture (i.e.: data and program share the same memory space). these processors have a cisc core ( complex instruction set com- puter ) with 63 instructions. these instructions are from 2 to 4 bytes long. the processor uses an accumulator called a. read access throughout the entire memory space is very easy. in consequence, the program memory can be efficiently used to store constant tables. 2.2 ram on the st72, the first 128 bytes of the ram array is call the zero page (addresses from $80 to $ff). the data in this zone can be accessed in short addressing mode (8-bit addresses) re- ducing the opcode size and speeding-up the access. this is not a bank system, because it is possible (but slower) to access the entire ram array using the long addressing mode (16-bit addresses). table 3. ram st7xxg1-2 256*8 with no bank switching pic16c62/72a 128*8 accessible through 2 banks of 128 bytes (the banks contain 96 bytes of user data and the hardware registers) pic16f873 192*8 accessible through 2 banks of 128 bytes (the banks contain 96 bytes of user data and the hardware registers) pic16f876 368*8 accessible through 4 banks of 128 bytes (the banks contain 96 bytes of user data and the hardware registers)
6/40 benchmark st72 vs. pic16 2.3 rom ? program memory access the pic16f87x allows the program to read or write program memory during normal execu- tion. 14 opcodes are needed to read one word (14-bit) and 23 opcodes to write one word. the mcu is halted during a write (10ms) and after it restarts with the next instruction. in the st72, read access to the program memory is very easy, but there is no write access al- lowed during execution. ? conclusion the two program memory organisations are quite different. a pic16 with 8k*14 of memory could be compared to a st72 with 16k*8 (which does not exist in 28 pins). but due to the risc instruction set of the pic16, more assembly instructions are needed to code the same program in the st72. table 4. rom st72254g1 4 k*8 (-> up to 2048 instructions) flash which can store either programs or data st72254g2 8 k*8 (-> up to 4096 instructions) flash which can store either programs or data pic16c62/72a 2k*14 (->really 2048 instructions) otp or eprom (uv erasable) pic16f87x 8k*14 (->really 8092 instructions) flash for program storage 256*8 eeprom for data storage. this eeprom is accessible only through an indexed mode (9 instructions are needed to read one eeprom byte)
7/40 benchmark st72 vs. pic16 2.4 frequency 2.5 voltage range ? conclusion the pic16f87x has a wider voltage range. it can work at 2.0 v but to take advantage of this voltage range, the operating frequency must be lowered to 4mhz. moreover, two different mcus are needed to cover the entire voltage range. for example: at 3.5v, the st72254 can work at full speed (16mhz) and the pic can run only at 4mhz. table 5. frequency pic16c62 / pic16f87x st72254 f oscilator max 20mhz 16mhz f cpu max 5mhz (fosc/4) 8mhz (fosc/2) f instruction max 5mhz (instructions are 1 or 2 cycles long) 4mhz (quickest instructions are two cy- cles long) 0 4 8 12 16 20 1,5 2 2,5 3 3,5 4 4,5 5 5,5 voltage (v) fosc (mhz) pic16lcx-04 pic16xcx-04 pic16 cx-20 pic16xc -xx 0 4 8 12 16 20 1,522,533,544,555,5 voltage (v) fosc (mhz) pic16lfx-04 pic16xfx-04 pic16 fx-20 pic16xf -xx 0 4 8 12 16 20 1,522,533,544,555,5 voltage (v) fosc (mhz) st7 pic16c62/72a 4.5 v - 5.5 v pic16lc62/72a 2.5 v - 5.5 v pic16f87x 4.5 v - 5.5 v pic16lf87x 2.0 v - 5.5 v st72254 3.0 v - 5.5 v
8/40 benchmark st72 vs. pic16 2.6 stack ? pic16 the stack is only 8 levels deep (it is like a 16 bytes deep stack) and is separated from the user ram. the stack cannot be accessed by software (no push or pop!). ? st72 the stack is up to 128 bytes deep, it can store 64 addresses. it shares the user ram. the stack can be easily accessed by software (push/pop instructions, stack pointer is r/w) 2.7 registers 2.7.1 code condition register vs. status register the two registers are nearly the same but the st72 has a negative bit to indicate if the result of the last operation is negative or not. 2.8 addressing mode the pic16 offers only 3 addressing modes (immediate, relative, indexed). the ram is or- ganised in banks of 96 bytes. this means that bank switching is needed to access the entire ram. the architecture of the pic does not allow programs to directly address flash or eeprom . the st72 is really more powerful . it has 11 different addressing modes. and it never needs bank switching. and, last but not least, it allows programs to access ram or flash (for reading) in exactly the same way. table 6. registers pic16 st72 accumulator w (8-bit) a (8-bit) program counter 13-bit (memory is organised in words of 14- bit) 16-bit (memory is organised in bytes) stack pointer not accessible 7-bit index register fsr (8-bit) needs bank switching two index register x,y: 8-bit
9/40 benchmark st72 vs. pic16 2.8.1 indexed mode the pic16 has one index register (fsr), but it works like a data memory location. this means that it is not possible to work directly with this register. the only operations which can be done without using the accumulator are: incrementation, decrementation and comparison with zero. consequently, table manipulations are quite hard to handle . the st72 has two index registers . the following operations on this register can be done di- rectly (without using the accumulator): incrementation, decrementation, comparison with a value and loading a value (literal or stored in a register) . 2.9 instruction set due to its risc architecture the pic16 s instruction set is very small, only 35 instructions . but these instructions are executed quickly (all need only one cpu cycle except branches which need two cycles). the internal clock is divided by 4. in consequence, compared to the st72 (where the clock is divided by 2) the instructions are like 2 or 4 cycle instructions of the st72. the st72 has a cisc architecture with 63 instructions (nearly twice as many as the pic). these instructions are one to four bytes long and need between 2 to 12 cpu cycles. the st72 has a multiplication instruction 8-bit*8-bit, result on 16-bits. this multiplication needs only 11 cpu cycles. to do the same with pic architecture, you need at least 37 cpu cycles and 35*14 bits of program memory (or 71 cpu cycles and 16*14 bits of memory).
10/40 benchmark st72 vs. pic16 2.10 interrupt *t instruction is the number of f cpu cycles needed to complete the current instruction ? pic16 during an interrupt, only the return address is automatically saved onto the stack. saving the context needs to be done manually (10 instructions needed) and the interrupt sub-routine must also restore the context (6 instructions needed). ? st72 the st72 has 7 different interrupt vectors, it allows you to easily create independent interrupt subroutines. context saving is done automatically. the only weak point of the interrupt mech- anism of the st72 is that the interrupt priority is fixed by hardware. but some st72s have a nested interrupt feature (ex: st72311r6) ? conclusion the interrupt response times are very much the same . but for marketing reasons, micro- chip does not take the time needed to save the context into account. this is why microchip an- nounces better response times. moreover, the pic architecture provides only one interrupt vector. so, the interrupt sub-routine has to read all the interrupt flags in order to find which in- terrupt needs to be serviced.this means a significant software overhead when many interrupt sources are used. table 7. interrupt sources/vectors pic16c62b pic16c72a pic16f87x st72254 it sources 7 8 13 19 it vectors 111 7 register saved no no no pc, x, a and cc table 8. interrupt reaction time pic16 st72 min max min max t instruction * 12212 t jump 2 2 10 10 t context saving 4 10 included in the jump total (t cpu ) 7141022 interrupt reaction time 1.4 m s 2.8 m s 1.25 m s 2.75 m s
11/40 benchmark st72 vs. pic16 2.11 power saving mode ? pic16 the pic16 has only one power saving mode: the sleep mode. in this mode the oscillator is shut off. any of the following events can cause a wake-up from sleep mode: n external reset n watchdog timer (in sleep mode a watchdog time-out does not reset the mcu) n interrupt (if the individual interrupt enable bit is set) n tmr1 interrupt (if the timer1 clock is an external clock or if it is its own oscillator) n capture mode interrupt n special event trigger (cf. a/d and timer1) n spi or i2c in slave mode n usart in slave mode (if available) n a/d conversion if a/d clk is rc n eeprom write complete the mcu needs 1024 t osc (256 cpu cycles) to wake-up (except in rc mode where the wake- up is immediate) ? st72 the st72 has three different power saving modes : n slow mode , which allows the internal clock of the device to be reduced (4 different speeds available) n wait mode , which turns off the cpu but keeps the clock active for the peripherals. it can be exited by any peripheral interrupt (ex: timer, spi...). wake-up from this mode is immediate. n halt mode , which turns off the cpu and the clock system. it can be exited by external interrupt. the cpu needs 4096 cpu cycles (8092 t osc ) to wake-up in order to stabilise the oscillator. ? conclusion with its three power saving modes, the st72 is quite flexible . it is possible to adjust the power consumption to the exact needs of the application. however, in situations when the pic16 sleep mode can be used, it might be more efficient. this is because serial communication is still possible in slave mode. in terms of current con- sumption, the pic16s sleep mode is not unlike the st72s halt mode. moreover, the pic16s wake-up is faster: 1024 osc illator cycles compared to 8 092 for the st72, and with an rc oscillator the pic16 is woken-up immediately but the st72 is not.
12/40 benchmark st72 vs. pic16 2.12 power consumption data (taken from the datasheet) *in rc mode the current through r is not included. *in rc mode the current through r is not included. table 9. pic16 power consumption data (low power device) pic16lf87x, pic16lc62b/72a low consumption devices pic16lf87x pic16lc62b/72a typ max typ max run mode ocs1=external square wave from rail to rail. all i/o tristated, pulled to v dd . /m clr pulled to v dd . v dd =3.0v xt mode, rc oscillator 4mhz (fcpu=1mhz)* 2ma 3.8ma 2ma 3.8ma lp mode, fosc=32khz (fcpu=9khz) wdt disabled 20ua 48ua 22.5ua 48ua power down current (sleep mode), all i/o in high impedance and tied to v dd or v ss . v dd =3.0v wdt enabled, -40c to +85c 7.5ua 30ua 7.5ua 30ua wdt disabled, -40c to +85c 0.9ua 5ua 0.9ua 5ua wdt disabled, 0c to +70c 0.9ua 5ua 0.9ua 5ua lvd add typ 85ua max 200ua of consumption (characterized but not tested) (vdd=5v) timer1 oscillator add approx 20ua (vdd=5v) table 10. pic16 power consumption data (standard device) pic16f87, pic16c62b/72a pic16f87x pic16c62b/72a typ max typ max run mode ocs1=external square wave from rail to rail. all i/o tristated, pulled to v dd . /m clr pulled to v dd . v dd =5.5v xt mode, rc oscillator 4mhz (fcpu=1mhz)* 2ma 5ma 2.7ma 5ma hs mode, fosc=20mhz (fcpu=5mhz) 10ma 20ma 10ma 20ma power down current (sleep mode), all i/o in high impedance and tied to v dd or v ss . v dd =4.0v wdt enabled, -40c to +85c 10.5ua 42ua 10.5ua 42ua wdt disabled, -40c to +85c 1.5ua 19ua 1.5ua 19ua wdt disabled, 0c to +70c 1.5ua 16ua 1.5ua 16ua wdt disabled, -40c to +125c 2.5ua 19ua 2.5ua 19ua lvd add typ 85ua max 200ua of consumption (characterized but not tested) timer1 oscillator add approx 20ua
13/40 benchmark st72 vs. pic16 ? conclusion in run mode, the st72254 draws less power than the pic16f876. 5.5ma versus 10ma and with the maximum values the difference is even bigger 10ma vs. 20ma. for the power saving modes, the conclusion is hard to establish because the modes available are quite different. table 11. st72254 power consumption data st72254 typ max run mode ocs1=external square wave. all i/os in input mode with a static value v dd or v ss . cpu running with memory access. fosc=16mhz (fcpu=8mhz) v dd =5v 5.5ma 10ma fosc= 8mhz (fcpu=4mhz) v dd =5v 3ma 6ma slow mode. all i/os in input mode with a static v dd or v ss value fosc=16mhz (fcpu=500khz) v dd =5v 0.7ma 1.4ma fosc= 8mhz (fcpu=250khz) v dd =5v 0.5ma 1ma wait mode. all i/os in input mode with a static v dd or v ss value (values are characterized but not tested) fosc=16mhz (fcpu=8mhz) v dd =5v 2ma 4ma fosc= 8mhz (fcpu=4mhz) v dd =5v 1ma 2ma slow wait mode. all i/os in input mode with a static v dd or v ss value fosc=16mhz (fcpu=500khz) v dd =5v 0.4ma 0.8ma fosc= 8mhz (fcpu=250khz) v dd =5v 0.2ma 0.4ma halt mode. all i/os in input mode with a static v dd or v ss value. lvd disabled 0.5ua 5ua
14/40 benchmark st72 vs. pic16 3 core performance comparison stmicroelectronics has developed two sets of test routines related to 8-bit and low-end 16-bit microcontroller applications to evaluate the computing performance of microcontroller cores . these routines have been implemented on st72254 and pic16f876 microcontroller units. - the first set of routines has been written in assembler language to optimize their implementation and focus on core performance, without being dependent upon compiler code transformation. - the second set tries to evaluate the performance of the two mcus and their respective c compilers . this benchmark uses a c language program, representative of an automotive application. the c compilers used were from hiware on the st72 and from hi-tech on the pic16. the speed of the two mcus has been compared in two ways: - firstly, at the maximum frequency commercially available on each mcu. this means at an external frequency of 16mhz on the st72 and of 20mhz on the pic16. - secondly, at the same current consumption level (10ma). * this value is determined by interpolation as you can see, to reach the same power consumption level on the two mcus, the pics run- ning frequency must be lowered to 10mhz (ext.) and the st72 can keep its maximum fre- quency of 16mhz (ext.). table 12. current consumption data (taken from datasheets) f ext f cpu consumption (max) st72254 16mhz 8mhz 10 ma run mode pic16c72a 20mhz 5mhz 20 ma run mode pic16c72a 10mhz *2.5mhz 10 ma run mode
15/40 benchmark st72 vs. pic16 3.1 assembler test routines overview the set of test routines is made of 8 assembly programs which cover all the typical needs of an mcu application. this routine tests only the core performance and does not include any peripheral management. table 13. assembler test routine overview ? notes on memory accesses used in the test routines: the size of the arrays manipulated by the test routines has been chosen in order to minimize ram bank switching on the pic16 processor. this means that the results do not include any overhead for memory bank switching on the pic16 mcu. but with the complexity- levels of real-world applications, the paginated memory can be a major source of time and code overhead. for the same reason on the st72 the data are placed in the zero page, allowing to use the short addressing mode. abbreviated name full name description features stressed string string search search a 16-byte string in a 128- character array in rom 8-bit data block manipulation string manipulation char character search search a byte in a 40-byte array in rom 8-bit data manipulation char manipulation bubble bubble sort sort of a one-dimension array of 10 16-bit integers 16-bit data manipulation integer manipulation blkmov block move move a 64-byte block from a place in ram to another 8-bit data block manipulation block move convert block translation translate a 80-byte block in a different format 8-bit data manipulation use of a lookup table shright 16-bit value right shift shift a 16-bit value five places to the right 16-bit data manipulation bit manipulation bitsrt bit manipulation set, reset, and test of 3 bits in a 128-bit array bit computation bit and 8-bit data manipulation 32div 32-bit by 16-bit division unsigned division of a 32-bit dividend by a 16-bit divisor bit manipulation 16-bit substraction 16mul 16-bit integer multiplication multiplication of two unsigned words giving a 32-bit result 16-bit data computation integer manipulation
16/40 benchmark st72 vs. pic16 3.2 assembler test results *the speed ratio is calculated as follows: (time pic16)/(time st72). so, a number higher than 1 means that the st72 is faster. - at their maximum frequency , we can see that the execution speed of the two mcus is truly comparable . even though, in this configuration the external frequency of the pic16 is higher (20mhz) than that of the st72 (16mhz). - at the same power consumption level, the st72254 is significantly better. in other words, for the same power consumption budget, the st72254 is nearly 2 times more powerful than the pic16f87x . table 14. execution speed at maximum frequency at a current of 10ma description pic16 @20mhz st72 @16mhz speed ratio st72/pic16* pic16 @10mhz st72 @16mhz speed ratio st72/pic16* string 371 s 282 s 1.32 741 s 282 s 2.63 search a 16-byte string in a 128-character array in rom char 84 s 57 s 1.49 169 s 57 s 2.98 search a byte in a 40-byte array in rom bubble 752 s 857 s 0.88 1504 s 857 s 1.76 sort of a one-dimensional array of 10 16-bit integers blkmov 154 s 121 s 1.28 308 s 121 s 2.55 move a 64-byte block from one place in ram to another convert 256 s 241 s 1.06 513 s 241 s 2.13 translate a 80-byte block into a different format shright 6 s 10 s 0.65 13 s 10 s 1.29 shift a 16-bit value five places to the right bitsrt 36 s 62 s 0.58 72 s 62 s 1.17 set, reset, and test of 3 bits in a 128-bit array 32div 124 s 222 s 0.56 248 s 222 s 1.12 unsigned division of a 32-bit dividend by a 16-bit divisor 16mul 41 s 18 s 2.29 72 s 18 s 4.58 multiplication of two unsigned words giving a 32-bit result avg. 203 s 208 s 0.98 406 s 208 s 1.95 average results
17/40 benchmark st72 vs. pic16 3.3 results analysis ? bit manipulation: the microchip architecture is very fast for bit manipulation. modifying one bit in a data byte can be performed in only 1 cpu cycle which means in 0.2s@20mhz. to do the same operation the st72 needs 5 cpu cycles (0.625s@16mhz). ? memory access: the pic16 is faster in direct addressing mode (1 cycle 0.2s@20mhz compared to 3 cycles 0.375s@16mhz). this is very useful for many parts of the application where variables are di- rectly used, for example in loop control. the indirect mode of the pic16 (needed for table or string manipulation) is very slow, because its index register cannot be loaded without losing the content of the accumulator. the st72 with its two index registers and its wider choice of addressing modes allows very easy (and fast) data manipulation. to summarize, when there is no need for indirect addressing, the pic16 runs faster. but for more complex algorithms the st72 is better (faster and easier to program). moreover, the test routines use only a small amount memory so, there is no problem of bank switching. but in a real (and large-sized) application, this could be a major limitation of the pic16 architecture. ? use of constant tables the pic16 cannot read the content of its rom directly, this means that, constant tables must be handled in a strange way. it needs a sub-routine call and a computed jump. this takes at least 6 cpu cycles (1.2s@20mhz). on the st72, the same operation needs 6 cpu cycles (0.625s@16mhz). moreover, due to the need for a 8-bit computed jump, reading a constant table bigger than 256 bytes needs more time and code on the microchip architecture. ? multiplication: here, the comparison is easy: the st72 has a 8-bit multiply instruction. the pic16 does not have any. doing multiplication entirely by software implies considerable time and code over- head.
18/40 benchmark st72 vs. pic16 3.4 c test routines overview the source program has been provided by a customer. it has 9 modules controlled by the main routine in file7.c. it uses all instructions usually found in c language programs. the source makes heavy use of unsigned char, bit and table manipulations. the modules are described in the following table. we have tried to highlight the main features of each module. note: number of lines: 1918. 3.4.1 modification of the source files the pic16 data memory is organised in banks which contains up to 96 bytes of ram. but, the hi-tech c compiler (pic16) does not distribute the variables automatically into these different banks. so, to make the compilation phase work, the sources files need to be modified . two files have been modified: file2.c and file2.h. the modifications consist of using the key- words bank1 and bank2 to place some of the variables in the different memory banks. for the st72 we have made two sets of sources. the first one called standard does not have any modifications . the second one called improved is modified to take more advan- tage of the use of the zero page. the only modified file is file2.h where two lines are added: #pragma data_seg short zeropage #pragma data_seg default in order to make heavily-used global variables directly accessible (in short addressing mode) table 15. module description module #lines description features stressed file1 204 after evaluation of a data by a switch, manipulation of global data and function calls (~100) switch/case processing function calls file2 538 definition of functions with data manipulation, for loop, while statement, if and switch uses loop statements arithmetic computation file3 93 definitions of 6 functions manipulating arrays, one function doing intensive calculation array manipulation bit calculation file4 251 mainly load of constant tables, and manipulation of structures at the end constant table manipulation structure use file5 164 exactly the same file than file8.c but using switch/case statement switch/case statement file6 68 if processing and bitwise computation bit manipulation and if use file7 133 the file contains the main, initialises data and calls functions in the other files function calls data initialisation file8 88 exactly the same file then file5.c if/else statements file9 34 signed char data computation signed data manipulation
19/40 benchmark st72 vs. pic16 3.5 c test results * these source files have been modified - in terms of execution speed, the results are the same as in the assembly routine test: the execution speed of the two mcus is truly comparable at their maximum frequency . and for the same power consumption budget, the st72 is nearly 2 times more powerful than the pic16. - in terms of program size: the reported size is between 20% and 30% higher on the st72 than on the pic16. but this is normal, because the memory of the pic16 is organised in words of 14 bits and not in bytes (8-bit) like on the st72. table 16. results st72 (standard) st72 (improved)* pic16* rom usage 7242 bytes 6849 bytes 5529 words of 14 bits ram usage 200 bytes 200 bytes 180 bytes execution time cpu cycle 96374 94312 62609 time at the maximum frequency 12.04ms@16mhz 11.78ms@16mhz 12.52ms@20mhz time at a 10ma current 12.04ms@16mhz 11.78ms@16mhz 25.04ms@10mhz
20/40 benchmark st72 vs. pic16 4 peripherals 4.1 i/o ports both pic16 and st72 propose i/o ports with individual direction control. both have 22 i/o pins. ? pic16f87x n port a (6 pins): analog input. ttl buffers except ra4 which has schmitt trigger input or open drain output (true open drain but limited to 8.4 v) n port b (8 pins): ttl buffer, input with pull-up (globally selectable) rb0 external interrupt pin. rb4->rb7: interrupt when a value on a pin changes (selectable globally on input pins). n port c: 8 pins with schmitt trigger input buffer, ttl output note: the interrupt-on-change is dedicated to interfacing a 4*4 keypad. it can be used to wake-up the cpu when a key is pressed. but if the interrupt occurs while a read is in progress on portb (even a bit set on a pin) the interrupt may not be taken into account. consequently, if the interrupt-on-change feature is used, reading portb must be avoided . ? st72254 for all i/o pins it is possible to individually choose between : n floating input n pull-up input with interrupt n push pull output n open drain output. the open drain outputs are limited to logic level. but there are 2 true open- drain pins. pic16f87x: all the ttl buffers can source/sink high current st7254: has 8 outputs able to sink high current. ? conclusion the st72 offers more flexibility in the i/o port configuration but the pic16 outputs can sink or source bigger currents. table 17. output voltage level pic16 st72 standard output st72 high sink output vol 0.6 v / 8.5ma 0.5 v / 2 ma, 1.3 v / 5ma 0.5 v / 8ma, 1.3v / 20ma voh v dd - 0.7 v / 3 ma v dd - 0.8 v / 2ma ,v dd -2 v / 5ma v dd - 0.8 v / 2ma ,v dd -2 v / 5ma
21/40 benchmark st72 vs. pic16 4.2 clock the st72 has a useful clock module. it ensures that the mcu will always run, even if the crystal has a problem. this security system can be a welcome feature for a lot of applica- tions.the st72 proposes also an internal rc oscillator which allows to reduce the need for ex- ternal components to the minimum. 4.3 timer table 18. clock characteristics pic16c62b/72a pic16f87x st72254 min max min max min max external clock 0 mhz 20 mhz 0 mhz 20 mhz 0 16 mhz quartz/ ceramic oscillator 0.1 mhz 20 mhz 20 mhz 1 mhz 16 mhz rc oscillator 0 mhz 4 mhz 1 mhz 14 mhz external r 3 k 100 k 3 k 100 k 22 k 47 k external c 20 pf 20 pf 0 470 pf internal rc no no typ: 4 mhz safe clock oscillator no no 250 khz 430 khz clock spikes filter no no yes with detection table 19. timer summary pic16f87 st72254 2 timers 8-bit 1 timer 16-bit 2 pwm (same frequency) or 2 ic (same time base) or 2 oc (same time base) or 1 pwm and 1 ic no simple way to access the 16-bit timer (12 instructions to read the timer ) 2 timers 16-bit 2 pwm and 2 ic or 1 pwm and 2 oc and 3 ic or 2 one pulse mode and 2 ic and 2 oc or 4 ic and 4 oc security system (latches the lsb after reading the msb)
22/40 benchmark st72 vs. pic16 ? pic it has 3 different timers but with some restrictions. n timer0 (8-bit) share its prescaler with the watchdog. the prescaler allows to choose between 8 different timer frequencies. internal or external clock (if the prescaler is used to increase the watchdog time-out there is no possibility to choose the timer0 frequency.) n timer1 (16-bit) has four prescaler values. internal or external clock (in asynchronous mode or in synchronous mode). dedicated oscillator (up to 200khz). n timer2 (8-bit) has three prescaler values. period register, in fact it is a compare register and when a match is detected, the timer is cleared. ccp module: it is a register which can be configured as an input capture register or as an output compare register or as a pwm duty cycle register ( it is an exclusive or! ). it is possible to automatically clear the timer when there is an output compare match (this pos- sibility is referenced in the microchip documentation as special-event trigger). n the pic16c62b has one ccp module so it is possible to do either one ic or one oc or one pwm. n the pic16c72a also seems to have only one ccp module but there are some mistakes in the microchip documentation. n the pic16f87x has two ccp modules so it is possible to do two pwms or two ics or ocs or to do a mix. the special event trigger of the second ccp module can clear timer1 and start an a/d conversion. table 20. pwm pic (fosc=20mhz) st7 (fosc=16mhz) maximum resolution 10-bit 16-bit possible frequencies at full resolution 33 maximum frequency at full resolution 19.53khz 61hz maximum frequency at 10-bit resolution 19.53khz 3.9khz resolution available at 1 khz 1024 8000 resolution available at 20khz 1000 200
23/40 benchmark st72 vs. pic16 the two ccp modules share the same timer resources, and there are also some major restric- tions due to the interaction between the two modules. the pic16 does not provide any security system for ensuring the integrity of reading or writing the 16-bit timer, which needs two 8-bit accesses. to secure the access to the ccp register (ic, oc or pwm), microchip proposes to first shut off the function of the ccp register then to do the access and finally to re-enable the ccp module. to directly read or write the 16-bit timer, microchip proposes the following sequence of code table 21. ccp module interaction (pic16f87x) ccpx mode ccpy mode restriction capture capture same time base capture compare same time base (the special event trigger clears the timer) compare compare same time base (the special event trigger clears the timer) pwm pwm same frequency! and same update rate pwm capture no problem pwm compare no problem table 22. example of code for accessing the 16-bit timer example 12-3: writing a 16-bit free running timer ; all interrupts are disabled clrf tmr1l ; clear low byte, ensures no ; rollover into tmr1h movlw hi_byte ; value to load into tmr1h movwf tmr1h, f ; write high byte movlw lo_byte ; value to load into tmr1l movwf tmr1h, f ; write low byte ; re-enable the interrupt (if required) continue ; continue with your code
24/40 benchmark st72 vs. pic16 this program is taken from a microchip application note. finally, reading the timer requires between 9 and 12 cpu cycles and 12 14-bit words of pro- gram memory table 23. example of code for accessing the 16-bit timer example 12-4: reading a 16-bit free running timer ; all interrupts are disabled movf tmr1h, w ; read high byte movwf tmph ; movf tmr1l, w ; read low byte movwf tmpl ; movf tmr1h, w ; read high byte subwf tmph, w ; sub 1 st read with 2 nd read btfsc status,z ; is result = 0 goto continue ; good 16-bit read ; ; tmr1l may have rolled over between the read of the high and low bytes. ; reading the high and low bytes now will read a good value. ; movf tmr1h, w ; read high byte movwf tmph ; movf tmr1l, w ; read low byte movwf tmpl ; ; re-enable the interrupt (if required) continue ; continue with your code
25/40 benchmark st72 vs. pic16 ? st72 the st72 has one or two 16-bit timers. the first timer (non-optional) can work with an external clock but the second one (optional) cannot. the two timers are really independent. the timer value cannot be set directly (just a clear is possible). each timer has n a prescaler which provides 3 different time bases n 2 input capture functions n 2 output compare functions n 1 pwm (use the 2 ocs) n 1 one pulse mode (use 1 ic and 1 oc) n 4 alternate functions on the i/o ports (ic1,ic2,oc1,oc2). the first timer may also use an external clock pin on the st72 with 2 16-bit timers, there are 4 ics, 4 ocs, 2 pwms (really independent) and 2 one-pulse modes. the st72 offers a simple security system for accessing the 16-bit register (timer, ic or oc): the access to the msb part disables the function or latches the lsb value until the access to the lsb part is performed. ? conclusion the pic16 offers a better pwm for frequencies over 3.9khz . at frequencies below this limit, the precision of the st72 pwm is better. moreover, the st72 offers two really independent pwms while the pic16 pwms are linked and must run at the same frequency. microchip has three timers, this would appear to be better than on the st72. but there are a lot of restrictions in the use of these timers. this means that with its two timers the st72 is more powerful . in fact, it depends on the exact needs of the application . if the application can deal with the interactions between the different modules, then it can take an advantage of the three timers available on the pic16.
26/40 benchmark st72 vs. pic16 4.4 wdt: watchdog timer ? pic16 it uses an internal dedicated rc oscillator. it shares an 8-bit prescaler with the timer0 module. so when using the prescaler to increase the time-out period of the watchdog, there is no possibility to change the timer0 (8-bit timer) frequency. the time-out period is between 7 and 33 ms without prescaler ( the variations are due to fre- quency variations of the rc oscillator between each device ). using the prescaler, 8 time-out values can be chosen giving a time-out period up to 7*128=896 ms or 33*128=4.2s regardless of fcpu. in sleep mode , the watchdog is still running. a watchdog time-out while the mcu is in sleep mode will wake-up the mcu (and not reset it). so this feature prevents erroneously putting the cpu in sleep mode. if the cpu is put back in sleep mode, the watchdog is automatically cleared. the wdt can only be cleared. so you cannot easily modify the time-out period during execution. ? st72 the watchdog timer is completely independent of the other timers. the time-out period can be chosen between 64 values . it goes from 1.5ms to 98.3 ms (with a 16mhz oscillator) in halt mode, the oscillator is shut off, so the watchdog is also shut off. it restarts when the mcu is woken-up. you can choose the value you want to load into the wdt. so you can easily choose the wdt time-out for the next block of instructions. ? conclusion the watchdog of the st72 allows the time-out period to be defined more precisely. but, the watchdog of the pic16 offers a protection against erroneously entering sleep mode. table 24. watchdog timer pic16 st72 timer source dedicated rc oscillator internal clock min time out between 7-30 ms (depending of the device) 1.5ms (16mhz osc.) max time out between 896ms-4.2s (depending of the device) 98.3ms (16mhz osc.) possible values 8 values using the timer0 prescaler 64 refresh method clear the timer can load any value in the timer power down mode the wdt can wake-up the cpu from sleep mode the wdt is stopped in halt mode
27/40 benchmark st72 vs. pic16 4.5 lvd: low voltage detector ? pic16 it offers a single level low voltage detector. the cpu is put in reset, when the voltage goes below the low-level value for more than 100 m s (min time to detect the low voltage). when v dd rises-up again, the cpu enters power-up reset mode. the power-up reset is active for at least 28ms. if v dd goes down again during this time then the power-up timer is cleared. ? conclusion the lvd module of the pic16 is limited because it can only be used in 5v operating mode. but if the application runs at 5v there is no significant difference between the two modules. table 25. low voltage detector pic16 st72 min max typ max selectable lvd yes (one level) yes (3 levels) reset release threshold 3.7 v 4.3 v 4.3 v (high) 3.9 v (med) 3.35 v (low) 4.5v(high) 4.05v (med) 3.45 v (low) reset generation threshold 3.7 v 4.3 v 3.85 v(high) 3.50 v (med) 3.00 v (low) 4.25 v (high) 3.80 v (med) 3.20 v (low) hystereris done by holding in reset state for a minimum time after v dd rises again 250 mv
28/40 benchmark st72 vs. pic16 4.6 adc: analog to digital converter the a/d conversion modules of the pic16 and of the st72 are based on the same a/d con- version method (successive approximations). the pic16c62b does not have any adc cell. test condition: pic : at v ref =v dd =5.12v st7: v dd =5v worst-case temperature, negative injection v dd =v dda =5v fcpu=8mhz f adc =8mhz all these values are guaranteed (maximum value). 4.6.1 features the pic16f87x offers the possibility to assign an i/o pin to be the high analog voltage ref- erence . this is not available on 28-pin versions of the st72. the pic16f87x adc can work when the mcu is in sleep mode , using the timer output compare function to start the a/d conversion. the timer is automatically cleared. when the conversion is ready, the mcu is woken-up. to provide the a/d clock, there is a built-in rc os- cillator (using the rc oscillator, the conversion time is 48 m s for the pic16f87). this feature provides a way to do a/d conversion at a fixed rate with a minimum software overhead. on the st72, this mechanism doesnt exist. but, in wait mode the a/d module is still able to work, so an output compare interrupt can be set to wake-up the mcu and then it can read the last converted value, and set the oc up again to finally go back in wait. the software overhead is slightly more significant. table 26. adc characteristics pic16c72a pic16f87 st72254 resolution 8-bit 10-bit 8-bit channel 556 conversion time (under a 10k source impedance) 20 m s20 m s 3 m s maximum conversion frequency 50khz 50khz 333khz voltage reference (full scale) v dd or v ref ( i/o pin )v dd total absolute error +-1 lsb +-1 lsb +-1 lsb integral linearity error +-1 lsb +-1 lsb +-0.5 lsb differential linearity error +-1 lsb +-1 lsb +-0.5 lsb full scale error +-1 lsb +-1 lsb +-0.5 lsb offset error +-1 lsb +-1 lsb +-0.5 lsb
29/40 benchmark st72 vs. pic16 ? conclusion the a/d module of the st72 is really better than the module of the pic16c72a (faster and more precise). but in comparison with the pic16f87, the conclusion is more difficult to establish . the pic16f87 a/d module has a better resolution and the automatic sample rate feature, but the st72 a/d module runs significantly faster. so the advantages depend on the application. 4.7 spi serial communication ? common features n clk edge and polarity select n interrupt on transfer complete n selectable baud rate n msb first transmission n single buffered transmission register n double buffered reception register n ss allows to select the active slave ? pic16 n receive overflow detection (in slave mode). n can work while in sleep (slave mode only), the mcu is woken-up by the it on transfer complete. n the spi and i2c cells of the pic share the same registers, so it is not possible to use the spi and the i2c simultaneously. ? st72 n write collision detection: if a write is made to the register before the transfer is complete. n mode fault detection: if the ss is pulled low while in master mode, it automatically switches from master to slave mode. n can work in wait mode (master or slave mode), the mcu is woken-up by the interrupt on transfer complete. but it cant work in halt mode.
30/40 benchmark st72 vs. pic16 *these baud rates use the timer2 output as baud rate generator. ? conclusion the two spis, are almost the same. the pic16 is faster in transmission but slower in reception . and timer2 is needed in order to obtain some baud rates. the pic16 does not allow the spi and the i2c to be used simultaneously . the pic16 provides a receive-overflow detection (reception of a new byte completed before reading of the previous). this can be very useful, and certainly more useful than the write col- lision detection of the st72. the st72 allows a lower spi speed, which could be useful with some slow peripherals. table 27. baud rate pic16 (f ext =20mhz) st72 (f ext =16mhz) master mode (see note) 5 mhz * 2.5 mhz 1.25 mhz * 625 khz 312,5 khz * 156 khz 2 mhz 1 mhz 500 khz 250 khz 125 khz 62.5 khz maximum in slave mode pic16c62/72a: 1.78mhz (1/(2.5tcpu+60ns) pic16f87x: 2.27mhz (1/(2tcpu+40ns) 4mhz (fcpu/2)
31/40 benchmark st72 vs. pic16 4.8 i2c serial communication the pic16c62b/72a doesnt support the i2c master mode (it can be emulated by software). they also dont support general calls. 4.8.1 common features: n 7-bit/10-bit addressing n end-of-byte transmission flag (with interrupt capability) n programmable address n general call support (st7 and pic16f87x) n standard and fast mode support (100khz and 400khz) n automatic acknowledge. n detection of transmission in progress (busy flag) n start/stop generation (master mode st7 pic16f87x) n stop detection with it (slave mode). n interrupt on reception of a good address. table 28. i2c characteristic pic16c62b/72a pic16f87 st72254 address 7-bit/10-bit speed standard and fast mode acknowledge automatic interrupt end-of-byte / stop detection / address match master/slave slave only master/slave master/slave general call support no yes yes multi-master mode no yes yes bus arbitration sw automatic write collision detection yes yes yes acknowledge detection yes yes and automatic acknowledge failure detection receive overflow detection yes no bus error detection no yes power down activity yes (in slave mode only) yes in wait mode but not in halt
32/40 benchmark st72 vs. pic16 ? pic16 n multi-master support but bus arbitration must be done by software (pic16f87x). n write collision detection: when a write is done while the previous byte is been shifted (master mode pic16f87x). n start detection with it (slave mode). n receive overflow detection (slave mode). n acknowledge reception detection. in sleep mode the mcu can be woken-up when receiving of a byte or when an address match is completed (in slave mode only). the pic16 does not allow the i2c and the spi to be used simultaneously . ? st72 n multi-master support with bus lost arbitration detection (arlo) n the acknowledge of a general call can be disabled n the acknowledge sending can be disabled (globally) n bus error detection : if a start or stop condition is issued during a byte transfer. n acknowledge failure detection : reception of something else when waiting for an acknowledge. n in wait mode, the i2c module continues to work normally (master or slave mode) and the mcu can be woken-up by any interrupt from the i2c module.
33/40 benchmark st72 vs. pic16 4.9 usart/sci serial communication (pic16f87x only) this device is present only on the pic16f87x. it is able to perform serial communications in the following modes: n asynchronous (full duplex) n synchronous C master (half duplex) n synchronous C slave (half duplex) n 8/9 bit reception mode n framing error detection n address detection n overrun error detection note: the st72254 does not have an sci, but some st72 devices have one (ex: st72331j2) table 29. sci baud rate in asynchronous mode standard baud rate fosc=20mhz fosc=16mhz real baud rate %error real baud rate %error 300 na na 1200 1221 +1.73 1202 +0.16 2400 2404 +0.16 2404 +0.16 9600 9469 -1.36 9615 +0.16 19200 19530 +1.73 19230 +0.16 76800 78130 +1.73 83330 +8.51 96000 104200 +8.51 na 300000 312500 +4.17 na
34/40 benchmark st72 vs. pic16 4.10 isp: in situ programming ? conclusion : compared to the isp of the pic16c62b/72a (old device), the st72s isp is far better be- cause, it does not need a special voltage supply. this point is very important in case of an ap- plication at +3v where the mcu must be powered at +5v for programming. for the pic16f87x it is possible to use the isp at any voltage in the v dd range, but bulk erasing can only work at +5v. the st72 isp is also about 6 times faster (for the same size of code). note: microchips isp is presented as a two-pin isp but in fact a third pin is needed to select the programming mode (and this is without counting the m clr , v dd , and gnd pins). table 30. isp characteristics pic16c62b/72a pic16f87 st72 memory eprom (otp / uv) flash flash isp yes yes (two modes) yes pin needed for isp 5455 pin used m clr , clock, data, v ss , v dd m clr , clock, data, v ss m clr , clock, data, v ss , pgm reset, clock, data, v ss , ip sel entering programming mode transition from 0v to +12v on m clr sequence applied to pgm while in reset sequence applied to ip sel while in reset supply voltage during programming +5v only (even if the board works at 3v) bulk erasing works only at +5v programming can be done at any voltage in the v dd range +5v only (even if the board works at 3v) no specific needs, programming and verifying can be done at any voltage in the v dd range supply voltage during verify verify needs to be done at the v dd min and the v dd max of the application not precised in the mi- crochip documentation +5v programming method program directly loaded into the eprom (opt/uv) program directly loaded into the flash program directly loaded into the flash first a program is load- ed in ram, then it is executed, and it takes in charge the flash programming programming timing 10 ms per 14-bit 15 ms per 16*8-bit code protection yes yes 1
35/40 benchmark st72 vs. pic16 4.11 in circuit debugging (pic16f87x only) it is available on the pic16f87x only. it uses the in situ programming serial interface (m clr , v dd , gnd, rb7 and rb6). the debugger functionality takes a part of the mcu resources for its own use: no further data is available in the microchip documentation at the time this document is written. 4.12 reset pin ? conclusion the st72 reset pin is more useful and secure . it allows you to easily put all the board in reset when the mcu generates a reset (internal or external). its internal pull-up reduces the number of external components. 4.13 package the smd version packages are the same for both (so28). for the dip package, the situation is different: microchip proposes a pdip28 package and st a sdip32 package. despite the fact that the st72 package has more pins, it is smaller but cannot be plugged on the standard test board table 31. resources used by the in circuit debugging i/o pins rb6,rb7 stack 1 level program memory last 100h words data memory not precised in the microchip documentation table 32. reset pic16 st72 direction input only bi-directional pin internal pull-up no yes pin filtered no. but schmitt trigger input. yes other can receive a +12v to en- ter isp mode (to be taken into account the reset pin must be pulled low for at least 20 m s)
benchmark st72 vs. pic16 36/40 5 device summary table 33. device summary pic16f87x st72254 architecture harvard risc von neuman cisc memory program memory ram data eeprom up to 8k*14 (really 8092 instructions) 368*8 accessible through 4 banks of 128 bytes 128*8 eeprom accessible only through an indexed mode. (9 instructions are needed do read one eeprom byte) 8k*8 (-> up to 4096 instructions) 256*8 with no bank switching stack 8*13 (cannot be accessed, no push or pop) 128*8 frequency external / internal 20mhz / 5mhz (f osc /4) 16 mhz / 8 mhz (f osc /2) instruction instruction time: min / max number of instruction multiplication / division number of addressing mode 0.2 m s / 0.4 m s 35 sw / sw 3 (indexed mode need bank switching) 0.250 m s / 1.5 m s 63 hw / sw 11 interrupt sources / vectors / priority register saved reaction time min / max 13 / 1 pc (the context is not automatically saved) 1.4 m s / 2.8 m s (this time take into account the code needed to save the con- text, the difference is mainly due to the number of registers saved) 19 / 7 pc, ccr, a, x 1.25 m s / 2.75 m s (the difference between these two times is mainly due to different instruction times) voltage range for fosc >4mhz : 4.5v-5.5v for fosc 4mhz : 2 v- 5.5 v 3 v - 5.5 v oscillator rc / ceramic / crystal rc / ceramic / crystal / internal clock security system (clk filter, safe oscillator) consumption typ / max (run mode) power saving mode 10ma/ 20ma @fext=20mhz one sleep mode 5.5ma / 10ma@fext=16mhz three power saving modes i/o direction control mode control output mode input mode power output individual global push-pull (except 1 pin true open-drain). floating / 8 pins may have internal pull-up all outputs are high sink: v ol =0.6v at 8.5ma individual individual push-pull / open-drain (logic level except 2 pins) floating / pull-up with interrupt normal outputs: v ol =0.5v at 2ma 8 high sink outputs: v ol =0.5v at 8ma
benchmark st72 vs. pic16 37/40 watchdog time out: min time / max time number of time out values other 7ms-30ms / 896ms-4.2s (depending of the device) 8 / (the prescaler is shared with timer0) dedicated on-chip rc. the wdt can wake-up the cpu when it is in sleep mode 1.5ms / 98ms (fosc=16mhz) 64 it is possible to load any value in the timer, to easily choose the time-out period timer timers pwm/ic/oc usable in the same time access to the 16-bit register pwm resolution: max / at 1khz/ at 20khz 2 8-bit timers / 1 16-bit timer 2 pwm (same frequency) or 2 ic (same time base) or 2 oc (same time base) or 1 pwm and 1 ic no simple way to access 16-bit timer (12 instructions to read the timer ) 10-bit / 1024 / 1000 2 16-bit timers 2 pwm and 2 ic or 1 pwm and 2 oc and 3 ic or 2 one pulse mode and 2 ic and 2 oc or 4 ic and 4 oc security system (latches of lsb after reading the msb) 16-bit / 8000 / 200 spi speed: master / slave 5 mhz / 4.1mhz receive overflow detection the pic does not allow to use simultaneously the i2c and the spi . 2 mhz / 4mhz writes collision detection: i2c speed / addressing mode multi-master / bus arbitration other 100 khz or 400 khz / 7-bit or 10-bit yes / sw receive overflow detection the pic does not allow to use simultaneously the i2c and the spi . 100 khz or 400 khz / 7-bit or 10-bit yes / hw bus lost arbitration detection bus error detection usart / sci mode (max speed) asynchronous (full duplex) (max 312kbit/s) synchronous (half duplex) (max 5000kbit/s) no adc resolution / channel / conversion time voltage reference 10-bit / 5 / 20 m s internal (v dd ) or external can work in sleep mode, using a on-chip rc and it to wake-up 8-bit / 6 / 3 m s internal (v dd ) lvd level hysteresis one level for 5v operating done by holding in reset state for a minimum time 3 levels 250mv of hysteresis reset the reset state is not visible externally the reset state is visible externally isp pins needed way to enter programming mode speed 5 or 6 (depending of the mode used) +12v on mclr or sequence on pgm 10ms to program 14-bit (one opcode) 5 sequence on ipsel 15ms to program 16*8-bit icd in circuit debugging yes no table 33. device summary pic16f87x st72254
benchmark st72 vs. pic16 38/40 6 weak / strong points table 34. weak / strong points pic16f87x st72254 core execution speed both mcu have the same execution speed at their maximum frequency ( pic@20mhz and st7@16mhz external freq. ) - average assembler benchmark speed ratio: 1.03 (st7 speed / pic speed) - c compiler benchmark speed ratio: 1.02 fast bit manipulation fast direct memory access => fast execution of small algorithms fast calculation (8-bit hw multiplication) fast and easy indirect memory management fast and easy constant table manipulation => fast and easy implementation of complex algorithms power consumption the spi or i2c are still working in sleep mode (for slave operations) ? only 1 low power consumption mode ?? to keep a timer active while in sleep, a dedicated oscillator is needed lower consumption about 2 times for the same speed 4 power saving modes (slow, wait, slow-wait, halt) instruction set instructions are single cycle (except branch which need 2 cycles) ? only 3 addressing modes ? manipulation of the only index register is not easy (no direct load of literal value) instructions are slower but they are more powerful (difference between risc/cisc) many addressing modes (11) with 2 index registers fast 8-bit hw multiplication stack ?? no software access ?? only 8 levels deep push/pop instructions, stack pointer is r/w 128 bytes deep ? the stack pointer cannot be used as an index register => allow recursive calls and heavy imbrication level ram more ram on the pic16f876 (368 bytes) ?? need bank switching (each bank contains up to 96 bytes of user ram) no bank switching eeprom allow to store permanent data (256 bytes) it is possible to read or write the program memory ? difficult read access to eeprom or flash (9 or 12 opcodes needed) direct read access to program memory ?? no way to store permanent data on the st72254 but some st7 have a 256-bytes eeprom ex: st72331j2 interrupt ? only 1 interrupt vector => software overhead to find the interrupt source ? no hardware context saving (need to be done by software) each peripheral has its own interrupt vector 7 different vectors => fast and easy interrupt management ? static priority, but some st7 have a nested interrupt feature ex.:st72311r6 clock ? rc oscillator usable up to only 4mhz (fcpu=1mhz) internal rc (4mhz) external rc oscillator usable up to 14 mhz (=> fcpu=7mhz) safe clock, clock filter, with clock spike detection => allow secure clock management for critical applications
benchmark st72 vs. pic16 39/40 timer 3 timers: one 16-bit and two 8-bit better pwm precision (max: 10-bit) for frequencies over 3.9khz the 16-bit timer can use a dedicated slow oscillator ?? to keep a timer active in sleep mode, a dedicated oscillator is needed. ? no easy way to access the 16-bit timer (12 opcodes to read the timer) ?? many interactions between the 3 timers: the 2 pwms must run at the same frequency the prescaler of timer0 is shared with the watchdog the output of timer2 is needed to generate some baud rates of the spi 2 true 16-bit timers no interaction between the 2 timers better pwm precision (max: 16-bit) for frequencies below 3.9khz secure and easy access to the 16-bit timer registers i/o high sink output for all pins => direct led driving ? only push-pull output mode available (except for two open-drain pins) ? when using the interrupt-on-change feature (pins rb4-7) reading portb must be avoided push pull or open drain output modes with individual control floating or internal pull-up input modes with individual control ? activation of the internal pull-up, active also activates the interrupt. ? only 8 high sink i/os spi reception overrun detection transmission speed up to 5mhz (@fosc=20mhz) ? reception speed only up to 2.27mhz (@fosc=20mhz) ? need timer2 output for some baud rate ?? can not be used at the same time as the i2c cell reception speed up to 4mhz (@fosc=16mhz) ? transmission speed only up to 2mhz (@fosc=16mhz) i2c reception overrun detection ?? can not be used at the same time as the spi cell multi-master support with hardware bus arbitration usart / sci present ?? no sci on the st72254. but some st7 have a sci cell ex: st72331j2 adc 10-bit resolution automatic sampling rate with low software overhead ? slow conversion (20s, up to 50khz) fast conversion (3s, up to 333khz) in system programming ?? fully functional at vdd=+5v only faster (about 6 times) works at any v dd level in circuit debugging present (but not yet fully described in the microchip documentation) ? no voltage range larger voltage range (2v-5.5v) ? 2 different devices in order to cover the entire voltage range ?? below 4.5v, the external frequency must be decreased to 4mhz between 3.5v and 5.5v the maximum frequency can be used (16mhz) ? smaller voltage range (3v-5.5v) table 34. weak / strong points pic16f87x st72254
40/40 benchmark st72 vs. pic16 "the present note which is for guidance only aims at providing customers with information regarding their products in order for them to save time. as a result, stmicroelectronics shall not be held liable for any direct, indirect or consequential damages with respect to any claims arising from the content of such a note and/or the use made by customers of the information contained herein in connexion with their products." information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without the express written approval of stmicroele ctronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics - all rights reserved. purchase of i 2 c components by stmicroelectronics conveys a license under the philips i 2 c patent. rights to use these components in an i 2 c system is granted provided that the system conforms to the i 2 c standard specification as defined by philips. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sin gapore - spain sweden - switzerland - united kingdom - u.s.a. http://www.st.com

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